1. Field
Various embodiments of the present invention relate to a semiconductor memory device, and more particularly, to a semiconductor device including stacked memory chips.
2. Description of the Related Art
Semiconductor devices include semiconductor memory devices such as a dynamic random access memory (DRAM), and are widely used in various electronic systems. As electronic systems are gradually scaled down and their performance is improved, semiconductor devices included in the electronic systems are continuously being developed to satisfy the operation speed and process capability (e.g., bandwidth) that are required in the electronic systems. Particularly, various technologies for the semiconductor memory devices are being researched and developed to store large-capacity data and process the data at a high speed.
Among the technologies is a high bandwidth memory (HBM) device. To develop a HBM device capable of processing large-capacity data at a high speed, memory chips are fabricated in high integration. That is, numerous memory cells are integrated and fabricated in a limited space of a semiconductor chip. However, there is a limitation in highly integrating the memory cells in terms of fabrication process technology. The limitation may be overcome by packaging the memory chips or dies in a three-dimensional (3D) structure in which the fabricated memory chips or dies are stacked.
A stacked package of the semiconductor memory device includes stacking two or more semiconductor chips vertically. For example, the stacked package of the semiconductor memory device may have at least twice as much memory capacity as the memory capacity that may be realized through a semiconductor integration process. However, a difference among the parameters of the semiconductor chips located at different slices may occur due to variations in the process, voltage, and temperature (PVT). For example, an AC parameter, such as address access delay time (tAA), which indicates the time from read command input to a data output, may vary, and consequently a skew occurs between data outputted from the different slices.
FIG. 1 is a block diagram illustrating a conventional semiconductor memory device. FIG. 1 shows a data output circuit of the semiconductor memory device in which three semiconductor chips are stacked.
Referring to FIG. 1, the semiconductor memory device includes one master chip 100 and two slave chips 200 and 300. The master chip 100 includes a pipe latch 120 and outputs data DATA1 and DATA2, which are transmitted through one channel from the slave chips 200 and 300, to a data pad DQ. A buffer (or transmitter) 110, 210, 220, 310, or 320 may be further included as an input or output circuit of each chip 100, 200, or 300.
The slave chips 200 and 300 output a control signal PIN together with the data DATA1 and DATA2 to the master chip 100 when the data DATA1 and DATA2 are outputted from a core region based on a read command. After latching the data DATA1 and DATA2 transmitted from the slave chips 200 and 300 based on the control signal PIN, the master chip 100 outputs the latched data DATA1 and DATA2 to the data pad DQ in time for column address strobe (CAS) latency. When there is no parameter difference between the slave chips 200 and 300 and no skew occurs between data which are outputted from the slave chips 200 and 300, the data transmitted through one channel are normally combined through the master chip 100. However, when there is the parameter difference between the slave chips 200 and 300, and a skew occurs between the data which are outputted from the slave chips 200 and 300, it is difficult for the master chip 100 to secure accurate eye patterns of the data transmitted through one channel.
An operation of the semiconductor memory device shown in FIG. 1 and related issues are described below in detail with reference to the timing diagrams of FIG. 2 illustrating output data.
FIG. 2 illustrates timing diagrams of the data outputted from the semiconductor memory device shown in FIG. 1. FIG. 2 shows a case (a) in which a skew does not occur between the data outputted from the slave chips and a case (b) in which the skew occurs between the data outputted from the slave chips.
Referring to FIG. 2, in case of (a), the data DATA1 and DATA2 are outputted from the first slave chip 200 and the second slave chip 300 at the same time based on read commands RD1 and RD2, and the data which are normally combined are outputted to the data pad DQ through one channel. However, in case of (b), the data DATA1 and DATA2 are outputted at different times due to the parameter difference between the first slave chip 200 and the second slave chip 300. For example, the first slave chip 200 outputs the data later than the second slave chip 300, and thus the data where the skew occurs are then outputted to the data pad DQ.